1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory transistor which is capable of mnimizing the area when adapted to the technology of a sub-micron.
2. Description of the Related Art
FIG. 1 is a cross sectional view for explaining the bias condition of an electrically erasable and programmable read only memory (EEPROM) structure manufactured according to the prior art.
The operation of the EEPROM structure for program, erase and read is shown in the following Table 1.
TABLE 1V_selectV_controlConditionV_draingategateV_sourceV_subMethodProgramGNDHigherHigher thanFloatingGNDF-Nthan ˜10 V˜10 VTunnelingEraseHigherHigherGNDFloatingGNDF-Nthan ˜10 Vthan ˜10 VTunnelingRead˜1 VVccVccGNDGND—
As shown in FIG. 1 and Table 1, high temperature electrons are implanted to poly-1 by the F-N tunnel method along a tunnel window by the bias applied upon programming. By this, the threshold voltage Vt is increased to form an off-transistor upon reading. Additionally, the high temperature electrons flow out from poly-1 by the F-N tunnel method along the tunnel window by the bias applied upon erasing, and thus the cell threshold voltage Vt is lowered to form a turn-on transistor.
In this way, an EEPROM cell having a select transistor has a relatively large unit cell area, thus, as the unit cell area is lowered to below sub-microns, the competitive power for cell size is lowered, so it is difficult to reduce the cell size.